Programmable logic devices are used for a wide variety of custom hardware development. These devices contain configurable logic and circuits that can be programmed to implement a wide range of custom hardware designs and functions.
The configurable logic circuits are made up of a sea of primitive digital and analog elements that can selectively be wired to each other to implement a desired function.
Programmable logic devices are commonly known by the acronyms “CPLD” (complex programmable logic device) and “FPGA” (field programmable gate array). CPLDs are smaller devices, capable of selecting 10's or 100's of individual logical and/or electrical elements. FPGAs are typically larger devices capable of implementing 10's of thousands to millions of logical and electrical elements.
Some of the design tools required to implement FPGAs are proprietary and can only be obtained from the FPGA vendors. The size and density of the largest FPGA devices coupled with proprietary tool flows creates problems unique to FPGAs.
The largest programmable logic device vendors: Xilinx®, Altera® and Lattice Semiconductor® produce a number of different programmable device “families,” each of which contain a number of different devices. Each device in a device family makes use of the same basic building blocks or primitive silicon elements such as programmable logical elements, phase locked loops, memories, I/O cells and other special purpose analog and digital circuits. The members in the device family vary the number of these primitive elements to provide a number of different cost alternatives based on required capacity of a user's designs.
For example, Xilinx® makes a range of devices in the Virtex®-5LXT family. This family contains members such as the XC5VLX30TFF323 and the XC5VLX330TFF1738. The XC5VLX30TFF323 has up to 172 I/O and 32 DSP blocks available to the user, whereas the XC5VLX330TFF1738 has up to 960 I/O and 192 DSP blocks available to the user. By the manufacturer's design, the electrical and logical functions the user can program into these I/O or implement with the DSP blocks are the same for the 2× devices. The manufacturer makes these functions identical for devices in the same device family so that a given design will operate the same in each device in the same family. This provides an upgrade path as the user's design grows in size, and re-usability of design components that target a specific device family.
In addition to primitive silicon elements, FPGA vendors offer pre-qualified macro designs for rapid development of popular logical and electrical functions. These macro designs are commonly referred to in the art as, “Intellectual Property” or “IP” blocks. These IP blocks are delivered to the user with functional models for the user to test their logical design's behavior and interaction with the IP blocks inside a logic simulation. In addition to the behavioral models, the IP block vendors provide physical models suitable for synthesis and place and route software to consume that are translated into physical implementations suitable to program into an FPGA device.
Design Process
The current state of the art for developing field programmable device designs is a serial, step-wise process. Generally accepted design flows follow a sequence of steps from register transfer level (RTL) coding or programming of hardware behavior to logic simulation to synthesis to place and route to hardware validation.
RTL coding is the process of describing logical design behavior by writing software files in a Hardware Description Language (HDL). Common HDL languages include very high speed integrated circuits (VHSIC) HDL (VHDL) and Verilog. This process requires the hardware designer to write code that captures desired behavior using a subset of the HDL language that is suitable for downstream processing. Downstream processes that consume RTL code include logic simulation and synthesis.
Logic simulation is a process that enables hardware designers to exercise their HDL design files with a software program. Simulator programs are intended to show the behavior of constructed hardware after it will be built. The simulators allow hardware designers to write tests and models to interact with their HDL designs and the logic simulator executes the tests against the HDL description of the design. Simulators include debugging tools that show signal behavior graphically as waveforms.
Synthesis is the process of converting HDL design files into a set of interconnected hardware primitives suitable to be placed inside a semiconductor device. This interconnected set of primitives is commonly called a netlist in the art. The conversion process requires the synthesis software to infer hardware elements from user supplied HDL code.
Synthesized netlists are passed to place and route tools. Place and route is the process of creating a 2× dimensional map of the primitives in the netlist and the wiring between them. This map corresponds to the spatial organization of components and wiring on the physical semiconductor device that implements the design. The outputs of place and route for FPGAs are files that are used to program the physical devices which implement the user's design.